A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters

DOI10.1109/TCSI.2010.2072130zbMath1468.94264OpenAlexW2162386400MaRDI QIDQ5010550

Kevin J. Wang, Ian Galton

Publication date: 26 August 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2010.2072130

Mathematics Subject Classification ID

Signal theory (characterization, reconstruction, filtering, etc.) (94A12)

This page was built for publication: A Discrete-Time Model for the Design of Type-II PLLs With Passive Sampled Loop Filters