Efficient Partial-Parallel Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes

DOI10.1109/TCSI.2010.2071830zbMATH Open1468.94474OpenAlexW2130240580MaRDI QIDQ5010565

Xinmiao Zhang, Fang Cai

Publication date: 26 August 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2010.2071830

Mathematics Subject Classification ID

Linear codes (general theory) (94B05) Decoding (94B35)

Related Items (5)

SCALABLE AND EFFICIENT IMPLEMENTATIONS OF THE LDPC DECODER USING RECONFIGURABLE MODELS ⋮ Fully Parallel Stochastic LDPC Decoders ⋮ An Efficient Partial-Sum Network Architecture for Semi-Parallel Polar Codes Decoder Implementation ⋮ Title not available (Why is that?) ⋮ Jointly Designed Nonbinary LDPC Convolutional Codes and Memory-Based Decoder Architecture

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