A High-Throughput LDPC Decoder Architecture With Rate Compatibility

DOI10.1109/TCSI.2010.2089551zbMath1468.94473OpenAlexW2115461214MaRDI QIDQ5010600

Zhongfeng Wang, Xinming Huang, Kai Zhang

Publication date: 26 August 2021

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2010.2089551

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Decoding (94B35)

Related Items (1)

High-throughput architectures for circular block-type low-density parity-check codes

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