Optimizing Data Intensive Flows for Networks on Chips

DOI10.1142/S0129626421500134zbMath1490.68036arXiv1812.07183MaRDI QIDQ5087092

Yang Liu, Thomas G. Robertazzi, Li Shi, Junwei Zhang

Publication date: 8 July 2022

Published in: Parallel Processing Letters (Search for Journal in Brave)

Full work available at URL: https://arxiv.org/abs/1812.07183

zbMATH Keywords

Voronoi diagrammeshdivisible load theorymulti-sourcedata-intensive loadload injectionnetwork on chip (NOC)

Mathematics Subject Classification ID

Graph theory (including graph drawing) in computer science (68R10) Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Mathematical problems of computer architecture (68M07) Flows in graphs (05C21)

Cites Work

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• Scheduling for parallel processing
• Performance limits of divisible load processing in systems with limited communication buffers
• Finding the Constrained Delaunay Triangulation and Constrained Voronoi Diagram of a Simple Polygon in Linear Time
• Scalable Hybrid Wireless Network-on-Chip Architectures for Multicore Systems

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