Verification of asynchronous circuits by BDD-based model checking of Petri nets

DOI10.1007/3-540-60029-9_50zbMath1496.68194OpenAlexW1595213177WikidataQ56893082 ScholiaQ56893082MaRDI QIDQ5096372

Oriol Roig, Enric Pastor, Jordi Cortadella

Publication date: 16 August 2022

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: http://hdl.handle.net/2117/133572

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85) Switching theory, applications of Boolean algebras to circuits and networks (94C11)

Related Items (4)

Rewriting semantics of production rule sets ⋮ A decision diagram operation for reachability ⋮ Hierarchical Set Decision Diagrams and Automatic Saturation ⋮ High level synthesis of synchronous parallel controllers

Cites Work

• Compiling communicating processes into delay-insensitive VLSI circuits
• Graph-Based Algorithms for Boolean Function Manipulation
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