SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS OF AND, NOT GATES

DOI10.17223/20710410/38/5OpenAlexW2778872026MaRDI QIDQ5151082

Kirill A. Popkov

Publication date: 16 February 2021

Published in: Prikladnaya diskretnaya matematika (Search for Journal in Brave)

Full work available at URL: http://mathnet.ru/eng/pdm602

zbMATH Keywords

stuck-at faultlogic networksingle fault detection test

Mathematics Subject Classification ID

Computer science (68-XX) Information and communication theory, circuits (94-XX)

Related Items (8)

The length of a single fault detection test for constant-nonpreserving element insertions ⋮ The length of single-fault detection tests with respect to substitution of inverters for combinational elements in some bases ⋮ Short single fault detection tests for logic networks under arbitrary faults of gates ⋮ A method of synthesis of irredundant circuits admitting single fault detection tests of constant length ⋮ Short single tests for circuits with arbitrary stuck-at faults at outputs of gates ⋮ Lower bound of the length of a single fault diagnostic test with respect to insertions of a mod-2 adder ⋮ The length of single fault detection tests with respect to substitution of gates with inverters ⋮ On self-correcting logic circuits of unreliable gates with at most two inputs

Cites Work

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• Lower estimate of the length of the complete test in the basis \(\{x|y \}\)
• On schemes admitting brief tests
• Synthesis of easily-tested circuits in the case of single-type constant malfunctions at the element outputs
• Complete tests for circuits of functional elements
• Circuits admitting single-fault tests of length 1 under constant faults at outputs of elements
• Method of synthesis of easily testable circuits admitting single fault detection tests of constant length
• Synthesis of easily testable circuits over the Zhegalkin basis in the case of constant faults of type 0 at outputs of elements
• On the synthesis of circuits admitting complete fault detection test sets of constant length under arbitrary constant faults at the outputs of the gates
• Easily Testable Realizations ror Logic Functions

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