Synthesis of easily testable logic networks under arbitrary stuck-at faults at inputs and outputs of gates

DOI10.17223/20710410/43/6zbMath1466.94070OpenAlexW2940341697MaRDI QIDQ5151257

Kirill A. Popkov

Publication date: 17 February 2021

Published in: Prikladnaya Diskretnaya Matematika (Search for Journal in Brave)

Full work available at URL: http://mathnet.ru/eng/pdm654

zbMATH Keywords

diagnostic testfault detection testlogic networkarbitrary stuck-at fault

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Switching theory, applications of Boolean algebras to circuits and networks (94C11)

Related Items (3)

The length of a single fault detection test for constant-nonpreserving element insertions ⋮ Short single fault detection tests for logic networks under arbitrary faults of gates ⋮ A METHOD FOR CONSTRUCTING LOGIC NETWORKS ALLOWING SHORT SINGLE DIAGNOSTIC TESTS

Cites Work

• On checking tests for schemes with constant faults on input of elements
• Easily Testable Realizations ror Logic Functions
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