Formal Verification of Floating-Point Hardware Design

DOI10.1007/978-3-030-87181-9zbMATH Open1486.68005OpenAlexW4214810372MaRDI QIDQ5159259

David M. Russinoff

Publication date: 26 October 2021

Full work available at URL: https://doi.org/10.1007/978-3-030-87181-9

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Research exposition (monographs, survey articles) pertaining to computer science (68-02) Mathematical problems of computer architecture (68M07)

Related Items (3)

Counterexample- and simulation-guided floating-point loop invariant synthesis ⋮ A formally verified floating-point implementation of the compact position reporting algorithm ⋮ A Mechanically Checked Proof of IEEE Compliance of the Floating Point Multiplication, Division and Square Root Algorithms of the AMD-K7^™ Processor

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