Joint Decoder Design for SSDs
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Publication:5238785
DOI10.1109/TSP.2019.2905822zbMATH Open1458.94328OpenAlexW2922084906MaRDI QIDQ5238785
Publication date: 28 October 2019
Published in: IEEE Transactions on Signal Processing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1109/tsp.2019.2905822
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