Optimization of manufacturing of emitter-coupled logic to decrease surface of chip

DOI10.1142/S021797921550023XzbMath1310.94238MaRDI QIDQ5249436

E. L. Pankratov, E. A. Bulaeva

Publication date: 6 May 2015

Published in: International Journal of Modern Physics B (Search for Journal in Brave)

zbMATH Keywords

optimization of technological processdecreasing surface of chipemitter-coupled logic

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

Cites Work

• A JASTROW CORRELATION FACTOR FOR TWO-DIMENSIONAL PARABOLIC QUANTUM DOTS
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