On the synthesis of circuits admitting complete fault detection test sets of constant length under arbitrary constant faults at the outputs of the gates

DOI10.1515/DMA-2013-024zbMath1329.94108OpenAlexW2335158186MaRDI QIDQ5249794

Publication date: 12 May 2015

Published in: Discrete Mathematics and Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1515/dma-2013-024

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Analytic circuit theory (94C05)

Related Items (10)

Estimations of the lengths of tests for logic gates in presence of many permissible faults ⋮ Complete Fault Detection Tests of Length 2 for Logic Networks under Stuck-at Faults of Gates ⋮ On the exact value of the length of the minimal single diagnostic test for a particular class of circuits ⋮ SINGLE FAULT DETECTION TESTS FOR LOGIC NETWORKS OF AND, NOT GATES ⋮ Lower bounds for the lengths of single tests for Boolean circuits ⋮ A method of synthesis of irredundant circuits admitting single fault detection tests of constant length ⋮ Short Complete Fault Detection Tests for Logic Networks with Fan-In Two ⋮ Short single tests for circuits with arbitrary stuck-at faults at outputs of gates ⋮ Lower bound of the length of a single fault diagnostic test with respect to insertions of a mod-2 adder ⋮ Synthesis of circuits admitting complete checking tests of constant length under inverse faults at outputs of elements

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