New Design for Testability Approach for Clock Fault Testing

DOI10.1109/TC.2011.59zbMath1365.94692MaRDI QIDQ5277620

Martin Omaña, T. M. Mak, Cecilia Metra, Simon Tam

Publication date: 12 July 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12) Reliability, testing and fault tolerance of networks and computer systems (68M15)

Related Items (1)

Localization of multiple faults with group control on a discrete device

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