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Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs - MaRDI portal

Architecture-Aware Technique for Mapping Area-Time Efficient Custom Instructions onto FPGAs

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Publication:5280588

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DOI10.1109/TC.2010.237zbMath1368.68023MaRDI QIDQ5280588

S. K. Lam, Christopher T. Clarke, Thambipillai Srikanthan

Publication date: 27 July 2017

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

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