Cryptographic Hardware and Embedded Systems - CHES 2004
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Publication:5311429
DOI10.1007/B99451zbMath1104.68499OpenAlexW2491896407MaRDI QIDQ5311429
Publication date: 23 August 2005
Published in: Lecture Notes in Computer Science (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/b99451
Related Items (14)
A First-Order Leak-Free Masking Countermeasure ⋮ Boosting Higher-Order Correlation Attacks by Dimensionality Reduction ⋮ Taylor Expansion of Maximum Likelihood Attacks for Masked and Shuffled Implementations ⋮ Higher-order masked Saber ⋮ Secure hardware implementation of nonlinear functions in the presence of glitches ⋮ Side-channel resistant crypto for less than 2,300 GE ⋮ Statistical properties of side-channel and fault injection attacks using coding theory ⋮ Multivariate high-order attacks of shuffled tables recomputation ⋮ Parallel Implementations of Masking Schemes and the Bounded Moment Leakage Model ⋮ Higher-Order Masking in Practice: A Vector Implementation of Masked AES for ARM NEON ⋮ On the Security of RSM - Presenting 5 First- and Second-Order Attacks ⋮ Secure Hardware Implementation of Non-linear Functions in the Presence of Glitches ⋮ Design of a Differential Power Analysis Resistant Masked AES S-Box ⋮ Formal Analysis of the Entropy / Security Trade-off in First-Order Masking Countermeasures against Side-Channel Attacks
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