Synthesis of Reactive Switching Protocols From Temporal Logic Specifications
From MaRDI portal
Publication:5353268
DOI10.1109/TAC.2013.2246095zbMath1369.93307WikidataQ59813902 ScholiaQ59813902MaRDI QIDQ5353268
Ufuk Topcu, Jun Liu, Richard M. Murray, Necmiye Ozay
Publication date: 8 September 2017
Published in: IEEE Transactions on Automatic Control (Search for Journal in Brave)
Related Items (19)
Quantitative Model Checking for a Controller Design ⋮ Robustly complete synthesis of sampled-data control for continuous-time nonlinear systems with reach-and-stay objectives ⋮ An improved algorithm for the control synthesis of nonlinear sampled switched systems ⋮ Closing the gap between discrete abstractions and continuous control: completeness via robustness and controllability ⋮ Finite abstraction of mixed monotone systems with discrete and continuous inputs ⋮ A Dynamical System for Prioritizing and Coordinating Motivations ⋮ Finite abstractions with robustness margins for temporal logic-based control synthesis ⋮ First steps toward formal controller synthesis for bipedal robots with experimental implementation ⋮ Divergent stutter bisimulation abstraction for controller synthesis with linear temporal logic specifications ⋮ Formal controller synthesis from specifications given by discrete-time hybrid automata ⋮ Set-based control for disturbed piecewise affine systems with state and actuation constraints ⋮ Temporal logic guided safe model-based reinforcement learning: a hybrid systems approach ⋮ On the existence of homoclinic orbits in \(n\)-dimensional piecewise affine systems ⋮ Modelling and supervisory control of hybrid dynamical systems via fuzzy \(l\)-complete approximation approach ⋮ Augmented finite transition systems as abstractions for control synthesis ⋮ Automated generation of dynamics-based runtime certificates for high-level control ⋮ A design of GPU-based quantitative model checking ⋮ Sampling polynomial trajectories for LTL verification ⋮ Formal synthesis of closed-form sampled-data controllers for nonlinear continuous-time systems under STL specifications
This page was built for publication: Synthesis of Reactive Switching Protocols From Temporal Logic Specifications
