Two-Bit Messages are Sufficient to Implement Atomic Read/Write Registers in Crash-prone Systems

DOI10.1145/2933057.2933095zbMath1373.68115arXiv1602.02695OpenAlexW2271769340MaRDI QIDQ5361960

Achour Mostefaoui, Michel Raynal

Publication date: 29 September 2017

Published in: Proceedings of the 2016 ACM Symposium on Principles of Distributed Computing (Search for Journal in Brave)

Full work available at URL: https://arxiv.org/abs/1602.02695

zbMATH Keywords

upper boundreliabilityasynchronous message-passing systemprocess crash failureatomic read-write registermessage typesequence number

Mathematics Subject Classification ID

Distributed systems (68M14) Reliability, testing and fault tolerance of networks and computer systems (68M15) Distributed algorithms (68W15)

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Communication Complexity of Wait-Free Computability in Dynamic Networks ⋮ Brief Announcement: The MBroadcast Abstraction ⋮ Time-efficient read/write register in crash-prone asynchronous message-passing systems

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