Low Jitter and Multirate Clock and Data Recovery Circuit Using a MSADLL for Chip-to-Chip Interconnection

DOI10.1109/TCSI.2004.838147zbMath1371.94698OpenAlexW2155694916MaRDI QIDQ5362877

S.-I. Liu, Rong-Jyi Yang, Hsiang-Hui Chang

Publication date: 4 October 2017

Published in: IEEE Transactions on Circuits and Systems I: Regular Papers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/tcsi.2004.838147

Mathematics Subject Classification ID

Analytic circuit theory (94C05)

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