High speed modular systolic array-based DTCWT with parallel processing architecture for 2D image transformation on FPGA
DOI10.1142/S0219691317500473zbMath1373.68465OpenAlexW2621183944MaRDI QIDQ5365371
S. S. Divakara, Cyril Prasanna Raj, Sudarshan Patilkulkarni
Publication date: 6 October 2017
Published in: International Journal of Wavelets, Multiresolution and Information Processing (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1142/s0219691317500473
parallel architecturesystolic arrayFPGA implementationpipelined architecturedual-tree complex wavelets
Computing methodologies for image processing (68U10) Numerical methods for wavelets (65T60) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07)
Uses Software
Cites Work
- Rational Coefficient Dual-Tree Complex Wavelet Transform: Design and Implementation
- Image processing with complex wavelets
- Wavelet Transforms in Image Processing
- Wavelet footprints: theory, algorithms, and applications
- The Double-Density Dual-Tree DWT
- Complex wavelets for shift invariant analysis and filtering of signals
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