SAT-Based Scalable Formal Verification Solutions

DOI10.1007/978-0-387-69167-1zbMath1138.68037OpenAlexW621300437MaRDI QIDQ5386252

Aarti Gupta, Malay K. Ganai

Publication date: 22 April 2008

Published in: Series on Integrated Circuits and Systems (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-0-387-69167-1

zbMATH Keywords

Model CheckingDistributed Model CheckingHybrid SAT SolverMulti-clock SystemsSynthesis for Verification ParadigmVerification of Embedded Memory System

Mathematics Subject Classification ID

Introductory exposition (textbooks, tutorial papers, etc.) pertaining to computer science (68-01) Specification and verification (program logics, model checking, etc.) (68Q60) Problem solving in the context of artificial intelligence (heuristics, search strategies, etc.) (68T20)

Related Items (6)

SAT-Based Model Checking ⋮ Formal verification of logical descriptions with functional uncertainty based on logarithmic encoding of conditions ⋮ Towards better heuristics for solving bounded model checking problems ⋮ Polynomial graph transformability ⋮ DPLL+ROBDD Derivation Applied to Inversion of Some Cryptographic Functions ⋮ Unnamed Item

Uses Software

• DiVer

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