Automating Verification of Loops by Parallelization

DOI10.1007/11916277_23zbMath1165.68405OpenAlexW1557508031MaRDI QIDQ5387902

Reiner Hähnle, Tobias Gedell

Publication date: 27 May 2008

Published in: Logic for Programming, Artificial Intelligence, and Reasoning (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/11916277_23

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical aspects of software engineering (specification, verification, metrics, requirements, etc.) (68N30)

Related Items

Verification by Parallelization of Parametric Code

Uses Software

• ESC/Java
• KeY