On an asymptotic formula for the maximum voltage drop in a on-chip power distribution network
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Publication:5389595
DOI10.1017/S0956792511000350zbMath1236.94091OpenAlexW2162227537MaRDI QIDQ5389595
Maria Aguareles, Josep Rius, Jaume Haro, Joan Solà-Morales
Publication date: 21 April 2012
Published in: European Journal of Applied Mathematics (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1017/s0956792511000350
Related Items (2)
The maximum voltage drop in an on-chip power distribution network: analysis of square, triangular and hexagonal power pad arrangements ⋮ Derivation of the maximum voltage drop in power grids of integrated circuits with an array bonding package
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