Linear-Size Log-Depth Negation-Limited Inverter for k-Tonic Binary Sequences

DOI10.1007/978-3-540-72504-6_55zbMath1200.94067OpenAlexW4235086921MaRDI QIDQ5425472

Hiroki Morizumi, Jun Tarui

Publication date: 13 November 2007

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-72504-6_55

zbMATH Keywords

circuit complexityinverternegation-limited circuit\(k\)-tonic

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25)

Related Items (1)

Negation-limited complexity of parity and inverters

This page was built for publication: Linear-Size Log-Depth Negation-Limited Inverter for k-Tonic Binary Sequences