Boolean Abstraction for Temporal Logic Satisfiability
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Publication:5429344
DOI10.1007/978-3-540-73368-3_53zbMath1135.68469OpenAlexW1537589219WikidataQ62041318 ScholiaQ62041318MaRDI QIDQ5429344
Viktor Schuppan, Alessandro Cimatti, Stefano Tonetta, Marco Roveri
Publication date: 29 November 2007
Published in: Computer Aided Verification (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-540-73368-3_53
Related Items (8)
Extracting unsatisfiable cores for LTL via temporal resolution ⋮ Tightening the contract refinements of a system architecture ⋮ Towards a notion of unsatisfiable and unrealizable cores for LTL ⋮ An explicit transition system construction approach to LTL satisfiability checking ⋮ Enhancing unsatisfiable cores for LTL with information on temporal relevance ⋮ Diagnostic Information for Realizability ⋮ SAT-based explicit \(\mathsf{LTL}_f\) satisfiability checking ⋮ Reactive synthesis with maximum realizability of linear temporal logic specifications
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