A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS

DOI10.1142/S1469026806002052zbMATH Open1143.68347OpenAlexW2030307920MaRDI QIDQ5434996

Haidar M. Harmanani, Hassan A. Salamy

Publication date: 14 January 2008

Published in: International Journal of Computational Intelligence and Applications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1142/s1469026806002052

zbMATH Keywords

embedded core testing

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20) Computer system organization (68M99)

Cites Work

• Open Shop Scheduling to Minimize Finish Time

Related Items (2)

Application of the simulated annealing local search technique to problems of redundancy elimination in functional and parametric tests of integrated circuits ⋮ Scheduling semiconductor multihead testers using metaheuristic techniques embedded with lot-specific and configuration-specific information

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