Development of tests for VLSI circuit testability at the upper design levels

DOI10.1134/S0005117910090110zbMath1215.94103OpenAlexW2062271116MaRDI QIDQ544693

A. V. Il'inkova, L. A. Zolotorevich

Publication date: 16 June 2011

Published in: Automation and Remote Control (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1134/s0005117910090110

Mathematics Subject Classification ID

Applications of design theory to circuits and networks (94C30)

Related Items (1)

Project verification and construction of superchip tests at the RTL level

Cites Work

• Switch-level VLSI quasistatic simulation methods: comparative accuracy of models
• Polynomially Complete Fault Detection Problems
• Diagnosis of Automata Failures: A Calculus and a Method

This page was built for publication: Development of tests for VLSI circuit testability at the upper design levels