Maurer computers for pipelined instruction processing

DOI10.1017/S0960129507006548zbMath1141.68010OpenAlexW2165072244MaRDI QIDQ5458071

C. A. Middelburg, Jan A. Bergstra

Publication date: 10 April 2008

Published in: Mathematical Structures in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1017/s0960129507006548

zbMATH Keywords

micro-architectures

Mathematics Subject Classification ID

Related Items (6)

Synchronous cooperation for explicit multi-threading ⋮ On the operating unit size of load/store architectures ⋮ On the expressiveness of single-pass instruction sequences ⋮ Simulating Turing machines on Maurer machines ⋮ A thread calculus with molecular dynamics ⋮ Thread algebra for noninterference

Cites Work

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• Program algebra for sequential code
• Program algebra with unit instruction operators
• Combining programs and state machines
• Thread algebra for strategic interleaving
• A theory of computer instructions
• Splitting bisimulations and retrospective conditions
• Module algebra
• Process algebra for synchronous communication
• A Theory of Communicating Sequential Processes
• Process Algebra
• A Theory of Computer Instructions

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