Automata and Logics for Timed Message Sequence Charts

DOI10.1007/978-3-540-77050-3_24zbMath1135.68496OpenAlexW1500730377MaRDI QIDQ5458842

S. Akshay, Benedikt Bollig, Paul Gastin

Publication date: 24 April 2008

Published in: FSTTCS 2007: Foundations of Software Technology and Theoretical Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-77050-3_24

Mathematics Subject Classification ID

Formal languages and automata (68Q45) Logic in computer science (03B70) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

Related Items

SMT-based scenario verification for hybrid systems, A concurrency-preserving translation from time Petri nets to networks of timed automata, Event clock message passing automata: a logical characterization and an emptiness checking algorithm, Checking conformance for time-constrained scenario-based specifications

Cites Work

• Event-clock automata: a determinizable class of timed automata
• A theory of timed automata
• A Kleene theorem and model checking algorithms for existentially bounded communicating automata
• Message-passing automata are expressively equivalent to EMSO logic
• A theory of regular MSC languages
• Weak Second‐Order Arithmetic and Finite Automata
• Matching Scenarios with Timing Constraints
• On Communicating Finite-State Machines
• A Logical Characterisation of Event Clock Automata
• Communicating Timed Automata: The More Synchronous, the More Difficult to Verify
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