Boosting AES Performance on a Tiny Processor Core

DOI10.1007/978-3-540-79263-5_11zbMath1153.68375OpenAlexW1496045316MaRDI QIDQ5458939

Stefan Tillich, Christoph Herbst

Publication date: 24 April 2008

Published in: Topics in Cryptology – CT-RSA 2008 (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/978-3-540-79263-5_11

zbMATH Keywords

hardware-software codesignAdvanced Encryption Standard8-bit microcontrollerinstruction set extensionsAVR architecture

Mathematics Subject Classification ID

Cryptography (94A60) Data encryption (aspects in computer science) (68P25)

Related Items (1)

Implementation of Symmetric Algorithms on a Synthesizable 8-Bit Microcontroller Targeting Passive RFID Tags

Cites Work

• Unnamed Item
• A Very Compact S-Box for AES
• VLSI Implementation of a Functional Unit to Accelerate ECC and AES on 32-Bit Processors

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