Limited width parallel prefix circuits

DOI10.1007/BF00127876zbMath1215.94093OpenAlexW2028539866MaRDI QIDQ547485

David A. Carlson, Binay Sugla

Publication date: 2 July 2011

Published in: The Journal of Supercomputing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf00127876

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Analytic circuit theory (94C05) Complexity and performance of numerical algorithms (65Y20)

Related Items (1)

Parallel prefix computation on extended multi-mesh network.

Cites Work

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• Efficient parallel algorithms for linear recurrence computation
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• Parallel Prefix Computation
• An Algorithm for Solving Linear Recurrence Systems on Parallel and Pipelined Machines
• A Regular Layout for Parallel Adders
• Time and Parallel Processor Bounds for Linear Recurrence Systems
• Size-time complexity of Boolean networks for prefix computations
• A Parallel Algorithm for the Efficient Solution of a General Class of Recurrence Equations

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