Correct Hardware Design and Verification Methods

DOI10.1007/11560548zbMath1159.68311OpenAlexW2483257485MaRDI QIDQ5493227

Orna Kupferman, Alon Flaisher, Doron Bustan, Orna Grumberg, Moshe Y. Vardi

Publication date: 20 October 2006

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/11560548

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Mathematical problems of computer architecture (68M07)

Related Items (14)

Functional Specification of Hardware via Temporal Logic ⋮ Coverage metrics for temporal logic model checking ⋮ Inherent Vacuity in Lattice Automata ⋮ On the Notion of Vacuous Truth ⋮ HRELTL: a temporal logic for hybrid systems ⋮ Synthesizing Non-Vacuous Systems ⋮ Towards a notion of unsatisfiable and unrealizable cores for LTL ⋮ Linear temporal logic symbolic model checking ⋮ Vacuity in practice: temporal antecedent failure ⋮ Timed vacuity ⋮ From Philosophical to Industrial Logics ⋮ From Monadic Logic to PSL ⋮ Vacuity in synthesis ⋮ Before and after vacuity

This page was built for publication: Correct Hardware Design and Verification Methods