Reveal: A Formal Verification Tool for Verilog Designs
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Publication:5505565
DOI10.1007/978-3-540-89439-1_25zbMath1182.68111OpenAlexW1644782203MaRDI QIDQ5505565
Zaher Andraus, Karem A. Sakallah, Mark H. Liffiton
Publication date: 27 January 2009
Published in: Logic for Programming, Artificial Intelligence, and Reasoning (Search for Journal in Brave)
Full work available at URL: https://doi.org/10.1007/978-3-540-89439-1_25
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