Generation of Fault Tests for Linear Logic Networks

DOI10.1109/T-C.1972.223433zbMath0229.94020OpenAlexW2094424823MaRDI QIDQ5638214

Melvin A. Breuer

Publication date: 1972

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1109/t-c.1972.223433

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Related Items (1)

Check of linear combination circuits

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