An Efficient Algorithm for Generating Complete Test Sets for Combinational Logic Circuits

DOI10.1109/T-C.1971.223123zbMath0232.94016MaRDI QIDQ5641077

Stephen S. Yau, Yushan Tang

Publication date: 1971

Published in: IEEE Transactions on Computers (Search for Journal in Brave)

Mathematics Subject Classification ID

Fault detection; testing in circuits and networks (94C12)

Related Items (4)

An efficient algorithm for calculating Boolean difference ⋮ Complete test-set generation for bridging faults in combinational-logic circuits ⋮ An efficient algorithm for single and multiple fault test sets generation ⋮ A graph-theoretic multiple logic fault analysis through petri-nets

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