Compact SD: a new encoding algorithm and its application in multiplication

DOI10.1080/00207160.2015.1119269zbMath1407.68581OpenAlexW2339987686MaRDI QIDQ5737882

Abdalhossein Rezai, Parviz Keshavarzi

Publication date: 30 May 2017

Published in: International Journal of Computer Mathematics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1080/00207160.2015.1119269

zbMATH Keywords

FPGAhardware implementationcomputer arithmeticmodular multiplicationsigned-digit representation

Mathematics Subject Classification ID

Number-theoretic algorithms; complexity (11Y16) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Numerical algorithms for computer arithmetic, etc. (65Y04)

Cites Work

• Adaptive \(m\)-ary segmentation and canonical recoding algorithms for multiplication of large binary numbers
• On the OBDD complexity of the most significant bit of integer multiplication
• Fast modular multiplication based on complement representation and canonical recoding
• A Parallel and Uniform $k$-Partition Method for Montgomery Multiplication
• Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures
• Fast exponentiation based on common-multiplicand-multiplication and minimal-signed-digit techniques
• A SIGNED BINARY MULTIPLICATION TECHNIQUE

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