Mapping dynamic programming onto a linear systolic array

DOI10.1007/BF00929926zbMath0721.90079MaRDI QIDQ5753763

V. K. Prasanna Kumar, Yu-Chen Tsai

Publication date: 1990

Published in: Journal of VLSI signal processing systems for signal, image and video technology (Search for Journal in Brave)

zbMATH Keywords

efficient implementationlinear arrayfault-tolerant wafer scale integration model

Mathematics Subject Classification ID

Dynamic programming (90C39) Cellular automata (computational aspects) (68Q80) Computational methods for problems pertaining to operations research and mathematical programming (90-08)

Related Items (1)

Mapping dynamic programming onto modular linear systolic arrays

This page was built for publication: Mapping dynamic programming onto a linear systolic array