A design of time-optimum and register-number-minimum systolic convolvers

DOI10.1016/0167-8191(89)90087-2zbMath0689.68072OpenAlexW2035816957MaRDI QIDQ582105

Hiroshi Umeo

Publication date: 1989

Published in: Parallel Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/0167-8191(89)90087-2

zbMATH Keywords

VLSI designsystolic arraypolynomial dividerreal-time pattern matchersystolic algorithmsystolic convolver

Mathematics Subject Classification ID

Analysis of algorithms and problem complexity (68Q25) Cellular automata (computational aspects) (68Q80)

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Parallel integration of ODEs based on convolution algorithms

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