Computation of phase detector characteristics in phase locked loops for clock synchronization

DOI10.1134/S1064562408040443zbMath1215.93046OpenAlexW2016007813MaRDI QIDQ5892533

Gennady Alekseevich Leonov

Publication date: 8 June 2011

Published in: Doklady Mathematics (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1134/s1064562408040443

zbMATH Keywords

clock synchronizationcomputation of phase detector characteristics

Mathematics Subject Classification ID

Design techniques (robust design, computer-aided design, etc.) (93B51)

Related Items (2)

Computation of the phase detector characteristic of a QPSK Costas loop ⋮ Computation of the phase detector characteristic of classical PLL

Cites Work

• STABILITY AND BIFURCATIONS OF PHASE-LOCKED LOOPS FOR DIGITAL SIGNAL PROCESSORS
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