A low power approach to floating point adder design for DSP application

DOI10.1023/A:1008140025773zbMath0972.68005OpenAlexW1516483814MaRDI QIDQ5932376

R. V. K. Pillai, S. Y. A. Shah, A. J. Al-Khalili, Dhamin Al-Khalili

Publication date: 7 May 2001

Published in: Unnamed Author (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1008140025773

zbMATH Keywords

floating point adderhigh performance

Mathematics Subject Classification ID

Mathematical problems of computer architecture (68M07)

This page was built for publication: A low power approach to floating point adder design for DSP application