Computational analysis of counter-based schemes for VLSI test pattern generation

DOI10.1016/S0166-218X(00)00259-6zbMath0980.68148WikidataQ127517107 ScholiaQ127517107MaRDI QIDQ5936462

Dimitri Kagaris, Spyros Tragoudas

Publication date: 2001

Published in: Discrete Applied Mathematics (Search for Journal in Brave)

zbMATH Keywords

test pattern generationVLSI

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35)

Cites Work

• Unnamed Item
• A deterministic built-in self-test generator based on cellular automata structures
• On the use of counters for reproducing deterministic test sets

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