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A compiler-friendly RISC-based digital signal processor synthesis and performance evaluation - MaRDI portal

A compiler-friendly RISC-based digital signal processor synthesis and performance evaluation

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Publication:5938756

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DOI10.1023/A:1008155718930zbMath0969.68662OpenAlexW1487747866MaRDI QIDQ5938756

Jongbok Lee, Wonyong Wung, Jiyang Kang

Publication date: 1 October 2001

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1008155718930

zbMATH Keywords

performance evaluation architecture synthesis code converter compiler-friendly digital signal processor

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Mathematical problems of computer architecture (68M07) Computer system organization (68M99)

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