A loop-based apparatus for at-speed self-testing

DOI10.1007/BF02943206zbMath0979.68006OpenAlexW1967976938MaRDI QIDQ5942702

Paul Y. S. Cheung, Xiao-Wei Li

Publication date: 9 September 2001

Published in: Journal of Computer Science and Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/bf02943206

zbMATH Keywords

BIST scheme

Mathematics Subject Classification ID

Reliability, testing and fault tolerance of networks and computer systems (68M15)

Cites Work

• Exploiting deterministic TPG for path delay testing
• BIST test pattern generators for two-pattern testing-theory and design algorithms

This page was built for publication: A loop-based apparatus for at-speed self-testing