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Designing run-time reconfigurable systems with JHDL - MaRDI portal

Designing run-time reconfigurable systems with JHDL

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Publication:5943325

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DOI10.1023/A:1008107104782zbMath0990.68596MaRDI QIDQ5943325

Peter Bellows, Brad Hutchings

Publication date: 14 August 2002

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

zbMATH Keywords

configurable computing FPGA-based systems

Mathematics Subject Classification ID

Computer science aspects of computer-aided design (68U07) Computing methodologies for image processing (68U10) Computing methodologies and applications (68U99)

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