A high speed reconfigurable firewall based on parameterizable FPGA-based content addressable memories

DOI10.1023/A:1011140512041zbMath0988.68010OpenAlexW1597405022MaRDI QIDQ5945704

Alistair A. McEwan, Jonathan Saul

Publication date: 22 July 2002

Published in: The Journal of Supercomputing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1011140512041

zbMATH Keywords

content addressable memory

Mathematics Subject Classification ID

Network design and communication in computer systems (68M10)

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