Parallel, pipelined and folded architectures for computation of 1-D and 2-D DCT in image and video codec

DOI10.1023/A:1011165524744zbMath0983.68262OpenAlexW1532874323MaRDI QIDQ5947745

Jian-Ming Tseng, Shen-Fu Hsiao

Publication date: 21 April 2002

Published in: Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1011165524744

zbMATH Keywords

image compressionVLSIparallel-pipelined architectures

Mathematics Subject Classification ID

Hardware implementations of nonnumerical algorithms (VLSI algorithms, etc.) (68W35) Computer system organization (68M99)

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