Overview on a formal model of architecture/circuit trade-offs for the implementation of fast processors

DOI10.1016/S0010-4655(01)00236-3zbMath0986.68907OpenAlexW2075403938MaRDI QIDQ5950535

Mauro Olivieri

Publication date: 18 December 2001

Published in: Computer Physics Communications (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1016/s0010-4655(01)00236-3

zbMATH Keywords

CPU architecturehigh-speed microprocessorsimplementation complexity

Mathematics Subject Classification ID

Computing methodologies and applications (68U99) Computer system organization (68M99)

Uses Software

• SimpleScalar

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