Hardware-efficient and highly reconfigurable 4- and 2-track fault-tolerant designs for mesh-connected arrays

DOI10.1006/JPDC.2001.1702zbMATH Open0999.68030OpenAlexW2090534049MaRDI QIDQ5959180

Nihar R. Mahapatra, Shantanu Dutt

Publication date: 2 December 2002

Published in: Journal of Parallel and Distributed Computing (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1006/jpdc.2001.1702

zbMATH Keywords

\(m\)-track models

Mathematics Subject Classification ID

Computer system organization (68M99)

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