A theory for co-scheduling hardware and software pipelines in ASIPs and embedded processors

DOI10.1023/A:1014050303852zbMath0989.68009OpenAlexW65039770MaRDI QIDQ5959837

No author found.

Publication date: 11 April 2002

Published in: Design Automation for Embedded Systems (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1023/a:1014050303852

zbMATH Keywords

instruction-level parallelismModulo-Scheduled Pipelines

Mathematics Subject Classification ID

Performance evaluation, queueing, and scheduling in the context of computer systems (68M20)

This page was built for publication: A theory for co-scheduling hardware and software pipelines in ASIPs and embedded processors