Advanced methods for equivalence checking of analog circuits with strong nonlinearities

DOI10.1007/S10703-009-0086-9zbMath1207.68210OpenAlexW2028924344MaRDI QIDQ5962119

Lars Hedrich, Sebastian Steinhorst

Publication date: 16 September 2010

Published in: Formal Methods in System Design (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/s10703-009-0086-9

zbMATH Keywords

formal verificationanalog circuitsequivalence checking

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60)

Cites Work

• The computation of Kronecker's canonical form of a singular pencil
• On simultaneous additive equations II.
• Unnamed Item

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