Automatic generation of verified concurrent hardware using VHDL

DOI10.1007/978-3-031-22476-8_4zbMath1528.68053MaRDI QIDQ6113900

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Publication date: 10 August 2023

Published in: Lecture Notes in Computer Science (Search for Journal in Brave)

zbMATH Keywords

CSPconcurrencyVHDLcode synthesis

Mathematics Subject Classification ID

Theory of programming languages (68N15) Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85)

Cites Work

• A refinement strategy for Circus
• CCSP: A formal system for distributed program debugging
• FDR3 — A Modern Refinement Checker for CSP
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