Towards automatic temporal logic verification of value passing process algebra using abstract interpretation

DOI10.1007/3-540-61604-7_76zbMath1514.68165OpenAlexW1500467934MaRDI QIDQ6162105

Stefania Gnesi, Diego Latella, Alessandro Fantechi

Publication date: 28 June 2023

Published in: CONCUR '96: Concurrency Theory (Search for Journal in Brave)

Full work available at URL: https://doi.org/10.1007/3-540-61604-7_76

Mathematics Subject Classification ID

Specification and verification (program logics, model checking, etc.) (68Q60) Models and methods for concurrent and distributed computing (process algebras, bisimulation, transition nets, etc.) (68Q85) Temporal logic (03B44)

Cites Work

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• Compositionality and bisimulation: A negative result
• Gate splitting in LOTOS specifications using abstract interpretation

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